Senior Design Verification Engineer

Senior Design Verification Engineer – 7+ Years Employment Type: FTC (1 year duration- Possibility renewable) Location: Sweden (Anywhere in Sweden is fine ) Work Mode: Onsite 5 days Mandatory Interview Process: Virtual Please find the bellow job spec

• 7+ years of hands-on experience in ASIC/SoC Design Verification using System Verilog and UVM.
• Strong experience developing UVM testbenches from scratch at IP, subsystem, and full-chip levels.
• Hands-on expertise in developing agents, drivers, monitors, scoreboards, reference models, sequences, and functional coverage.
• Experience developing Verification IPs (VIPs) from scratch and/or integrating and customizing third-party VIPs, especially PCIe and AXI.
• Strong experience implementing SystemVerilog Assertions (SVA) for protocol, functional, and corner-case verification.
• Proven experience in functional/code coverage closure, coverage merging, constrained-random testing, and regression automation.
• Strong debugging skills with experience identifying RTL/testbench issues and driving verification signoff.
• Proficiency in Python/Perl/Shell/Tcl for regression and verification automation; experience with VCS/Verdi, Xcelium, or Questa is preferred.
• Experience developing tests from scratch, including directed, random, error-injection, stress, and corner-case scenarios.
• Ability to lead 5–8 engineers, review verification architecture/code, mentor junior engineers, and drive project execution and closure.